This invention relates generally to phase locked loop circuitry, and more particularly the invention relates to phase locked loop circuitry for providing a clock signal which is synchronous with data that is encoded by non-uniformly spaced data pulses.
Phase locked loop circuits are utilized in tape and disk drives to recover clock information necessary for the reading of data from the data storage medium. Sample and hold type phase comparators are typically employed in generating clock signals from encoded data having non-uniform data patterns. Further, the comparators compensate for variations in the speed of the storage medium.
U.S. Pat. No. 4,644,420 discloses a digital phase locked loop oscillator that provides a constant loop gain independent of the encoded data. The phase locked loop has a sample and hold phase comparator which utilizes a voltage controlled oscillator running at 32 times the data rate. However, such an oscillator frequency is beyond the practical limits of existing integrated circuit technologies.
The present invention is a phase locked loop circuit which recovers a clock from non-uniformly spaced data pulses using digital circuitry which is compatible with existing integrated circuit technology.